An typical active-matrix type liquid crystal display combined with an active-matrix type driver circuits on a same substrate will be described. For forming driver circuits on the same substrate of a display panel, the polysilicon TFTs are applied in manufacture processes. In the past, polysilicon TFTs (thin-film transistors) formed on an insulating substrate required expensive quartz substrates owing to the high-temperature processes involved in manufacture. Such TFTs have been applied to display panels of small size, and high added value and expensive.
That was followed by the development of techniques for forming a pre-film by low-pressure (LP) CVD (chemical vapor deposition), plasma (P) CVD or sputtering, etc., and annealing the pre-film using a laser to thereby form a polycrystalline, namely techniques whereby a polysilicon TFT can be formed at low temperature such that a glass substrate or the like can be used.
At the same time, advances have been made in techniques for forming oxide films, techniques for micro-manufacturing, and circuit design techniques. As a result, it has become possible to form polysilicon TFT display panels for mobile telephones, mobile information terminals and notebook personal computers. These display panels have peripheral circuits of the display panel integrated on the same substrate on which pixels are formed.    Patent Document 1 (Japanese Patent Kokai Publication No. JP2004-046054A) can be mentioned as a specific example.
FIG. 16 is a block diagram illustrating an example of the configuration of the display system of a liquid crystal display device combined with a driver circuit disclosed in Patent Document 1.
In this liquid crystal display device combined with driver circuits, as shown in FIG. 16, an active-matrix display area 110, in which pixels of M rows and N columns are arrayed in the form of a matrix, a row-direction scan circuit [scan line (gate-line) driver circuit] 109, a column-direction scan circuit (data-line driving circuit) 3504, an analog switch 3505 and a level shifter 3503 are formed integrally by polysilicon TFTs on a display device substrate 101.
A controller 113, a memory 111, a digital/analog converter (DAC) circuit 3502 and a scan circuit/data register 3501, etc., are mounted external to the display device substrate 101 in the form of an integrated circuit chip (IC chip) which is formed on a wafer of monocrystalline silicon. The analog switch 3505 has outputs the number of which is the same as the number N of column-direction data lines of the active-matrix display area 110.
Further, the liquid crystal display devices combined with driver circuits composed of polysilicon TFTs also include devices formed in combination with more complicated circuits, such as a DAC circuit.
FIG. 17 is a block diagram illustrating an example of the typical configuration of the display system of a liquid crystal display device having a built-in DAC circuit.
In the liquid crystal display device having the built-in DAC circuit, the following circuits are formed on the display device substrate 101 in addition to the active-matrix display area 110, in which pixels of M rows and N columns are arrayed in the form of a matrix, the row-direction scan circuit 109 and a column-direction scan circuit 3506 similar to those of the device in FIG. 16 not having the built-in DAC circuit: a data register 3507, a latch circuit 105, a DAC circuit 106, a selector circuit 107 and a level shifter/timing buffer 108.
According to this arrangement, the controller IC mounted externally of the display device substrate 101 does not include the DAC circuit, which uses a high voltage, and the memory 111, an output buffer 112 and the controller 113 can all implemented by low-voltage circuit and elements. As a result, the IC can be fabricated without making joint use of a high-voltage process that makes it necessary to generate a voltage signal for the purpose of writing signals to liquid crystal. This means that the cost is kept below that of the above-mentioned IC having a DAC as shown in FIG. 16.
The liquid crystal display device set forth above is thin and light in weight. This feature is exploited to mount such liquid crystal display devices on mobile information processing equipment.
The liquid crystal display described above is an example of a display device combined with driver circuits having the CMOS (Complementary Metal-Oxide Semiconductor) configuration. Owing to use of the CMOS configuration, a shift register circuit constituting the above-mentioned row-direction scan circuit 109 or column-direction scan circuit 3506 can be realized by a static circuit that employs an inverter circuit and clock inverter circuit.
A display device combined with a drive circuit is not limited to one based upon a CMOS-type TFT circuit. There has also been proposed a display device combined with a drive circuit composed of so-called single-channel TFTs, which is composed of TFTs only of NMOS-type or only of PMOS-type. In comparison with a CMOS-based TFT circuit, a single-channel TFT circuit uses a smaller number of layers. This makes it possible to reduce the number photomasks and to shorten manufacturing time. As a result, the cost of device manufacture can be reduced in comparison with the CMOS-based TFT circuit.
<Two-Clock Arrangement>
An arrangement disclosed in Patent Document 2 (Japanese Patent Kokai Publication No. JP2004-78172A) illustrates an example of a circuit using the above-mentioned single-channel TFTs. FIG. 18 is a block diagram of a shift register according to Patent Document 2 (Japanese Patent Kokai Publication No. JP2004-78172A); FIG. 19 is a diagram illustrating the specific circuitry of the shift register of Patent Document 2 (Japanese Patent Kokai Publication No. JP2004-78172A); FIG. 20 is an output waveform diagram of the shift register of Patent Document 2 (Japanese Patent Kokai Publication No. JP2004-78172A); and FIG. 21 is a waveform diagram useful in describing driving waveforms based upon the shift register of Patent Document 2 (Japanese Patent Kokai Publication No. JP2004-78172A).
As illustrated in FIG. 18, the shift register has nine cascade-connected stages (SRH1 to SRH9). That is, each stage has an output terminal (OUT) connected to an input terminal (IN) of the next stage.
The nine stages include eight stages (SRH1 to SRH8) corresponding to data-line blocks, and one dummy stage (SRH9). Each stage has the input terminal (IN), the output terminal (OUT), a control terminal (CT), a clock input terminal (CK), a first power-supply voltage terminal (VSS) and a second power-supply voltage terminal (VDD).
The eight stages (SRH1 to SRH8) supply block selection terminals of data-line blocks (BL1 to BL8) with block-selection start signals (DE1 to DE8), respectively. The block-selection start signals are enable signals of the line blocks.
The operation of each stage will be described with reference to FIGS. 19, 20 and 21.
FIG. 19 shows the circuit configuration of a Nth stage the shift register 164 in FIG. 18. In FIG. 19, a GOUT[N−1] is a signal supplied from a (N−1)th stage of the shift register, wherein in case of N=1, GOUT[N−1] is STH in FIG. 18). A GOUT[N+1] is an output signal from a (N+1)th stage, and a GOUT[N] is an output signal output of the Nth stage of the shift register, Responsive to the rising edge of a scan start signal (STV) which is supplied to the gate (N1) of a transistor M3 of a pull-up driver 173 through the input terminal (IN), the transistor M3 is turned on to charge a capacitor (C) of a pull-up circuit 171. By the way, the scan start signal (STV) in FIG. 20 corresponds to the signal STH supplied to the first stage SRH1 of the shift register 164 in FIG. 18. As a result, a pull-up transistor M1 is turned on and a high-level interval of a first clock (CKV) appears at the output terminal.
When the high-level interval of the clock signal appears at the output terminal (OUT in FIG. 18, which corresponds to a GOUT[N] in FIG. 19), the output voltage is boot-strapped in the capacitor (C) and the gate-line driving voltage of the pull-up transistor M1 rises above the turn-on voltage (VON).
Meanwhile, before input of a start signal, a first node (N1) is set to a second power-supply voltage (VON) by a sixth transistor M6 of a pull-down driver 174, whereby a second transistor M2 is turned on. Accordingly, the voltage of the output signal at the output terminal (OUT in FIG. 18, which corresponds to a GOUT[N] in FIG. 19) is at the state of the first power-supply voltage (VOFF). When the scan start signal (STV) is input, a seventh transistor M7 is turned off.
When the potential at a second node (N2) starts rising through the sixth transistor M6, a fourth transistor M4 starts turning on, whereby the voltage charged in the capacitor (C) starts discharging through the fourth transistor. As a result, the pull-up transistor M1 also starts turning off. The output signal GOUT(N+1) of the next stage which is supplied to the control terminal of fifth transistor M5 then rises to the turn-on voltage. The fifth transistor M5, therefore, turns on.
Further, the second node (N2) turns on and the output terminal OUT falls to the turn-off voltage (VOFF) owing to the turn-on voltage (VON).
By virtue of the above-described operation, each of the stages operates and output signals GOUT[1] to GOUT[4] are generated successively in such a manner that operation is stabilized.
<Four-Clock Arrangement>
Patent Document 3 (Japanese Patent Kokai Publication No. JP2000-155550A) discloses a circuit of the kind shown in FIG. 22 as a circuit arrangement controlled by four clock signals (C1 to C4). The arrangement comprises a first NMOS transistor T1 to a sixth NMOS transistor T6 and capacitors CAP1, CL1 and C12. Operation of the circuit will be described with reference to FIGS. 22 and 23.
When a high level is attained at a first node P1, a transistor T5 turns on. If clock signal C1 rises to the high logic level under these conditions, an output line 14i charges the high-level voltage of clock signal C1 supplied via the drain and source of transistor T5.
When the high-level clock signal C1 is supplied to the output line 14i, the capacitor CAP1 raises the voltage of the first node P1 up to the voltage level of the clock signal C1. Owing to an increase in the gate voltage by the capacitor CAP1, the transistor T5 transfers the high-level clock signal C1 to the output line 14i without attenuating the signal.
When the clock signal C1 transitions from the high to a low level, the voltage of the output line 14i also similarly transitions to a low level. This is ascribable to the fact that the transistor T5 is held in the turned-on state by the potential at the first node P1.
Next, when clock signal C3 transitions from the low to the high level, a transistor T3 turns on in such a manner that the voltage at node P2 will have a high level.
The transistor T2 also is turned on by the high-level voltage at the second node P2 supplied to its own gate, thereby discharging the electric charge on the first node P1 to VSS which is connected to VSSL.
Similarly, with regard to a transistor T6, the output signal of output line 14i falls to a low level in response to a high level at the second node P2 supplied to the gate of transistor T6.
[Patent Document 1]    Japanese Patent Kokai Publication No. JP2004-046054A (pp. 31-32, FIGS. 37, 38)
[Patent Document 2]    Japanese Patent Kokai Publication No. JP2004-78172A (pp. 36-37, FIGS. 5-9)
[Patent Document 3]    Japanese Patent Kokai Publication No. JP2000-155550A (p. 27, FIGS. 1, 2, 3)
The entire disclosures of Patent Documents 1 to 3 are incorporated by reference into the present application. The analysis described below is given by the present invention.
The above mentioned examples have the problems set forth below.
<Problem With Two-Clock Arrangement>
In the case of the arrangement disclosed in Patent Document 2 (Japanese Patent Kokai Publication No. JP2004-78172A), it is necessary to hold the transistor M2 in FIG. 19 in an ON state in order to maintain GOUT[N] in an OFF state. Further, after the potential at node N2 is reset to a high level by GOUT of the next stage following its own output, it is necessary to hold node N2 at a high level until the timing at which the next output is made. With this arrangement, the potential at node N2 gradually falls from a high level owing to leakage current of transistor M7 whose source and drain are connected to node N2.
Consequently, the current driving capability of transistor M2 declines, as a result of which it is difficult to hold GOUT[N] in an OFF state. That is, the gate of transistor M1 is placed in an open state.
Under these conditions, the potential at the gate of transistor M1 is subjected to fluctuations owing to the pulse of the signal CKV or CKVB connected to the source of transistor M1. As a consequence, the signal CKV or CKVB is output from GOUT[N] as GOUT[N] as is.
That is, in Patent Document 2, erroneous operation in which an output is produced at a timing at which output is unnecessary is brought about by leakage current from the transistor.
In particular, since a thin-film transistor that has been fabricated on a glass substrate uses a glass substrate that is permeable to light, optical leakage current due to irradiation with light also is produced.
Further, in a case where use is made of a polysilicon layer that has undergone re-crystallization by irradiating a silicon layer serving as a channel portion with an excimer laser, for example, variations in the size and density of the recrystallized crystal grains occur. This leads to fluctuations in transistor characteristics.
When it is attempted to implement the circuit of Patent Document 2 using thin-film transistors, therefore, there are cases where the circuit malfunctions owing to the fluctuation in transistor characteristics.
<Problem With Four-Clock Arrangement>
Next, in the case of Patent Document 3 (Japanese Patent Kokai Publication No. JP2000-155550A), it is necessary that the first node P1 and second node P2 be held at low and high levels, respectively, in order to maintain the OFF state of the output 14i in FIG. 22. That is, it is necessary that transistor T5 whose gate is connected to the first node P1 be set in an OFF state and that transistor T6 whose gate is connected to the second node P2 be set in an ON state.
There is a possibility that the potential at the second node P2 will gradually decline from a high level owing to fluctuations in the characteristics of transistor T4 or T3. The arrangement of FIG. 22 resets the second node P2 to a high level using the clock signal C3, as illustrated in FIG. 23, in order to deal with the fluctuation factor. Such an operation makes it possible to suppress malfunction due to floating of the second node P2.
With the arrangement of Patent Document 3, however, a separate problem arises, namely an increase in the number of clock signals. Consequently, because the arrangement described in Patent Document 3 is implemented by thin-film transistors, either the problem of circuit malfunction due to fluctuations in transistor characteristics or the problem of an increase in number of clock signals is the result.